Title :
Routing considerations in symbolic layout synthesis
Author :
Liao, Youlin ; Chow, Stan
Author_Institution :
Cadence Design Systems, Inc., San Jose, CA, USA
Abstract :
The authors discuss routing styles, including a newly proposed hybrid routing style, in basic silicon-level design for a symbolic layout synthesis tool with practical considerations for design rules and process technology. Methods for systematically adding jogs in the layout to achieve high layout quality are proposed. Algorithms for input/output-pin assignment and for pin-ordering routing that achieve a minimal number of vias are also presented. Experiments on real industry designs showed promising results
Keywords :
CMOS integrated circuits; circuit layout CAD; network routing; CMOS designs; design rules; input/output-pin assignment; jogs; pin-ordering routing; process technology; routing styles; silicon-level design; symbolic layout synthesis; vias; Design optimization; Hybrid power systems; Libraries; Process design; Rivers; Routing; Stacking; Strips; Synthesizers; Wires;
Conference_Titel :
Design Automation Conference, 1992. Proceedings., 29th ACM/IEEE
Conference_Location :
Anaheim, CA
Print_ISBN :
0-8186-2822-7
DOI :
10.1109/DAC.1992.227799
