• DocumentCode
    3257785
  • Title

    Efficiency of remote access caches in future SMP-based CC-NUMA multiprocessors: initial results

  • Author

    Moreno, Edward D. ; Kofuji, Sergio T.

  • Author_Institution
    LSI-EPUSP, Sao Paulo Univ., Brazil
  • fYear
    1997
  • fDate
    18-20 Dec 1997
  • Firstpage
    190
  • Lastpage
    197
  • Abstract
    The paper evaluates the benefits of adding a shared remote access cache (RAC) in SMP based CC-NUMA multiprocessors. We consider symmetric multiprocessor (SMP) nodes as the building blocks for a multiprocessor due to its cost effectiveness, which makes SMP nodes an attractive choice for CC-NUMA designers. We base our experimental evaluation of the future architectures on realistic hardware parameters for state of the art systems components. What distinguishes our work from previous research is that we consider future processors and adequate values to access time to memory/caches/RACs, network and SMP bus speed. We simulate six applications from the SPLASH-2 benchmark suite to compare the performance application of our baseline architecture (current machines) and future architectures (approach-1: slow network and approach-2: fast network) when RACs are used in the system. The simulation results show that for a 32-processor system based on four-processor SMP nodes, the RACs improve the overall system performance by up to 32%, 28% and 20% for our baseline, approach-1, and approach-2, respectively. Similarly, the RACs diminish the execution time by up to 35%, 28.2% and 22% for two-processor SMP nodes. Therefore, our principal conclusion is that RACs reduce the execution time in future systems which have four or two 500 MHz processors per node
  • Keywords
    cache storage; multiprocessing systems; parallel architectures; performance evaluation; storage management; 32-processor system; SPLASH-2 benchmark suite; approach-1; approach-2; baseline architecture; cost effectiveness; execution time; fast network; four-processor SMP nodes; future SMP based CC-NUMA multiprocessors; future architectures; performance application; realistic hardware parameters; shared remote access cache; slow network; state of the art systems components; symmetric multiprocessor nodes; two-processor SMP nodes; Circuit synthesis; Computer architecture; Delay; Feeds; Hardware; Memory architecture; Microprocessors; Multiprocessor interconnection networks; Random access memory; System performance;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Parallel Architectures, Algorithms, and Networks, 1997. (I-SPAN '97) Proceedings., Third International Symposium on
  • Conference_Location
    Taipei
  • ISSN
    1087-4089
  • Print_ISBN
    0-8186-8259-6
  • Type

    conf

  • DOI
    10.1109/ISPAN.1997.645092
  • Filename
    645092