DocumentCode
3257885
Title
Superpipelined control and data path synthesis
Author
Prabhu, Usha ; Pangrle, Barry M.
Author_Institution
Dept. of Comput. Sci., Pennsylvania State Univ., University Park, PA, USA
fYear
1992
fDate
8-12 Jun 1992
Firstpage
638
Lastpage
643
Abstract
The authors describe a superpipelined control and data path synthesis system. The system can handle pipelined modules in the data path, perform functional pipelining in the data path, and schedule the data path using a pipelined controller. Three control styles-serial, parallel, and pipelined-were implemented. The system automatically picks one depending on the data path, the clock frequency, and the functional unit and control path delays. The results showed that using a modifiable clock cycle time and a parameterized control style can significantly improve the throughput of high-performance systems
Keywords
circuit CAD; logic CAD; pipeline processing; FIR filter; Mark 1 processor; clock frequency; data path synthesis; functional pipelining; high level synthesis; high-performance systems; modifiable clock cycle time; parameterized control style; pipelined controller; superpipelined control; throughput; Automatic control; Clocks; Computer science; Control system synthesis; Control systems; Delay; High level synthesis; Pipeline processing; Processor scheduling; Throughput;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 1992. Proceedings., 29th ACM/IEEE
Conference_Location
Anaheim, CA
ISSN
0738-100X
Print_ISBN
0-8186-2822-7
Type
conf
DOI
10.1109/DAC.1992.227807
Filename
227807
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