Title :
Superpipelined control and data path synthesis
Author :
Prabhu, Usha ; Pangrle, Barry M.
Author_Institution :
Dept. of Comput. Sci., Pennsylvania State Univ., University Park, PA, USA
Abstract :
The authors describe a superpipelined control and data path synthesis system. The system can handle pipelined modules in the data path, perform functional pipelining in the data path, and schedule the data path using a pipelined controller. Three control styles-serial, parallel, and pipelined-were implemented. The system automatically picks one depending on the data path, the clock frequency, and the functional unit and control path delays. The results showed that using a modifiable clock cycle time and a parameterized control style can significantly improve the throughput of high-performance systems
Keywords :
circuit CAD; logic CAD; pipeline processing; FIR filter; Mark 1 processor; clock frequency; data path synthesis; functional pipelining; high level synthesis; high-performance systems; modifiable clock cycle time; parameterized control style; pipelined controller; superpipelined control; throughput; Automatic control; Clocks; Computer science; Control system synthesis; Control systems; Delay; High level synthesis; Pipeline processing; Processor scheduling; Throughput;
Conference_Titel :
Design Automation Conference, 1992. Proceedings., 29th ACM/IEEE
Conference_Location :
Anaheim, CA
Print_ISBN :
0-8186-2822-7
DOI :
10.1109/DAC.1992.227807