Inductance tolerance analyses and design-process map of embedded planar spiral inductor

Inductors can be fabricated directly on chip or on ceramic and organic substrates to enhance the performance of mobile and RF devices. Inductors fabricated on chip are more precise with tighter tolerances, but are more costly. Inductors fabricated on organics are lower in cost, but have higher tolerances owing to higher tolerances in fabrication processes. Inductance simulations and experiments were conducted in this investigation to examine the dependences of inductance on geometric factors. Planar spiral inductors with different line width (100-400 μm), coil pitch (100-400 μm) and number of turns (4-8) were simulated. Selected inductor configurations were fabricated on FR4 substrates using standard patterning and etching processes. Analysis revealed that etching has a pivotal influence on inductance tolerance. On this basis, a new normalizing procedure is developed to relate the inductor structure, inductance and inductance tolerance to fabrication process precision. The methodology is summarized in an inductor design-process map to facilitate the design of inductors on organic substrates and is illustrated in application case study. With the map, inductors can be designed to have specific level of tolerance with less design-prototyping cycles.