DocumentCode :
3257968
Title :
Hardware architecture and FPGA implementation of a parallel elitism-based compact genetic algorihm
Author :
Jewajinda, Yutana ; Chongstitvatana, Prabhas
Author_Institution :
Nat. Electron. & Comput. Technol. Center, Nat. Sci. & Technol. Dev. Agency, Bangkok, Thailand
fYear :
2009
fDate :
23-26 Jan. 2009
Firstpage :
1
Lastpage :
6
Abstract :
This paper presents hardware architecture and FPGA implementation of a parallel genetic algorithm called elitism-based compact genetic algorithm (EC-CGA). EC-CGA uses the probability model migration instead of migrating individuals in the population. The performance of the EC-CGA is enhanced by elitism-based approach. We propose scalable hardware architecture for the EC-CGA. The highly parallelized hardware units support scalable number of variables and precision. The benchmark problems and experimental results show the significant performance improvement.
Keywords :
field programmable gate arrays; genetic algorithms; parallel architectures; EC-CGA; FPGA; hardware architecture; parallel elitism-based compact genetic algorithm; probability model migration; Computer architecture; Concurrent computing; Distributed processing; Evolutionary computation; Field programmable gate arrays; Genetic algorithms; Genetic engineering; Hardware; Pipelines; Workstations; FPGA; Genetic algorithms; Hardware;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
TENCON 2009 - 2009 IEEE Region 10 Conference
Conference_Location :
Singapore
Print_ISBN :
978-1-4244-4546-2
Electronic_ISBN :
978-1-4244-4547-9
Type :
conf
DOI :
10.1109/TENCON.2009.5396138
Filename :
5396138
Link To Document :
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