Circuit structure relations to redundancy and delay: the KMS algorithm revisited

K. Keutzer et al. (see IEEE Trans. on Comput.-Aided Des., vol.10, no.4, p.427-35 (1991)) have presented an algorithm, known as the KMS algorithm, that derives an equivalent irredundant circuit implementation from a given redundant high-performance circuit, with no increase in delay measured using viability analysis. The authors resolve the main bottlenecks in the KMS algorithm, arising due to an iterative loop of timing analysis, gate duplications, and redundancy removal. A circuit structure property based on path lengths is related to testability and delay. Based on this relationship, an efficient implementation of the KMS algorithm is presented. It consists of the transformation of any Boolean network to an equivalent circuit structure on which a single redundancy removal achieves the same effect as the original KMS algorithm