A parallel image compression system for high-speed cameras

Author

Nishikawa, Yukinari ; Kawahito, Shoji ; Inoue, Takeru

Author_Institution

Graduate Sch. of Electron. Sci. & Technol., Shizuoka Univ., Hamamatsu, Japan

fYear

2005

fDate

38485

Firstpage

53

Lastpage

57

Abstract

In this paper, we propose a parallel image compression system for high-speed cameras. The proposed compression circuits are based on a 4×4-point 2-dimensional DCT using a DA method, zigzag scanning of 4 blocks of the 2-D DCT coefficients and a 1-dimensional Huffman coding. The compression engine is designed with FPGAs, and the hardware complexity is compared with JPEG algorithm. It is found that the proposed compression circuits require much less hardware, leading to a compact high-speed implementation of the image compression circuits using parallel processing architecture. The PSNR of the reconstructed image using the proposed encoding method is better than that of JPEG at the region of low compression ratio.

Keywords

Huffman codes; data compression; discrete cosine transforms; field programmable gate arrays; image coding; image reconstruction; parallel architectures; video cameras; 1-dimensional Huffman coding; 4×4-point 2-dimensional DCT; DA method; FPGA; discrete cosine transform; encoding method; field programmable gate array; high-speed camera; image reconstruction; parallel image compression system; parallel processing architecture; zigzag scanning; Algorithm design and analysis; Cameras; Circuits; Discrete cosine transforms; Engines; Field programmable gate arrays; Hardware; Huffman coding; Image coding; Transform coding;

fLanguage

English

Publisher

ieee

Conference_Titel

Imaging Systems and Techniques, 2005. IEEE International Workshop on

Print_ISBN

0-7803-8922-0

Type

conf

DOI

10.1109/IST.2005.1594527

Filename

1594527