Capacitive Gate Insulator Thickness and Its Impact on Static and Dynamic Behavior of Scaled PD-SOI-MOSFET

Author

Herrmann, T. ; Klix, W. ; Stenzel, R. ; Feudel, T. ; Hoentschel, J. ; Horstmann, M.

Author_Institution

Appl. Sci. Univ., Dresden

Volume

2

fYear

2006

fDate

27-29 Sept. 2006

Firstpage

345

Lastpage

348

Abstract

The influence of technological parameters on the capacitive gate insulator thickness and the electrical transistor behavior of different technology nodes were simulated. Starting from calibrated PD-SOI-transistors, designed for the 130 nm technology, scaled 45 nm technology transistors were examined. The inverter propagation delay time and corresponding saturation drive currents of different technologies with varying gate insulator thicknesses were compared under the aspect of manufacturability. Further improvements due to the implementation of metal gates were estimated

Keywords

MOSFET; delays; invertors; silicon-on-insulator; 130 nm; 45 nm; capacitive gate insulator thickness; dynamic behavior; electrical transistor behavior; inverter propagation delay time; saturation drive currents; scaled PD-SOI-MOSFET; static behavior; Annealing; Charge carrier density; Dielectrics and electrical insulation; Inverters; MOSFETs; Manufacturing processes; Propagation delay; Quantum capacitance; Silicon on insulator technology; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

International Semiconductor Conference, 2006

Conference_Location

Sinaia

Print_ISBN

1-4244-0109-7

Type

conf

DOI

10.1109/SMICND.2006.284015

Filename

4063243