DocumentCode
3258249
Title
Partitioning by regularity extraction
Author
Rao, D. Sreenivasa ; Kurdahi, Fadi J.
Author_Institution
Dept. of Electr. & Comput. Eng., California Univ., Irvine, CA, USA
fYear
1992
fDate
8-12 Jun 1992
Firstpage
235
Lastpage
238
Abstract
The authors present a general methodology for extracting regularity at any level of hierarchy, and explore the problem of digital system partitioning by extraction of regularity. They consider system-level partitioning to demonstrate that regularity can lead to reduced design costs. The digital system is modeled with cyclic directed graphs. A prototype system based on these ideas has been built. Some examples are discussed
Keywords
circuit layout CAD; directed graphs; cyclic directed graphs; digital system partitioning; general methodology; prototype system; regularity extraction; system-level partitioning; Circuit testing; Cost function; Design automation; Digital systems; Hardware; Power generation economics; Prototypes; System testing; Systolic arrays; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 1992. Proceedings., 29th ACM/IEEE
Conference_Location
Anaheim, CA
ISSN
0738-100X
Print_ISBN
0-8186-2822-7
Type
conf
DOI
10.1109/DAC.1992.227830
Filename
227830
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