High-level synthesis with pin constraints for multiple-chip designs

The authors describe an approach to multi-chip data path synthesis, given a behavorial description which has already been partitioned into a number of clusters, with the feasibility of clusters determined. The problem is divided into interchip connection determination and scheduling. A heuristic search technique is described for interchip connection determination. A pipelined RTL design consisting of multiple chips was produced by the software. A set of communication buses among the chips was determined, and the values to be transferred were scheduled on the pins and buses. The RTL design produced satisfied user-supplied constraints, including the number of input-output pins on individual chips