An enhanced parallel toroidal lattice architecture for large scale neural networks

Summary form only given, as follows. An enhanced parallel toroidal lattice architecture for neurocomputers is proposed. The performance of the architecture is almost proportional to the number of node processors. It uses the most efficient two-dimensional processor connections implemented by the VLSI technology to date and also has even greater expandability of performance and capacity of neurocomputers. The authors define the general neuron model that is the basis of the toroidal lattice architecture. Then they take a multilayer perceptron (MLP) as a typical example of neural networks and describe the simulation of the MLP using error backpropagation learning algorithms on virtual processors with the toroidal lattice architecture. Then, mapping from the virtual processors to physical node processors with the same toroidal lattice architecture is done by row and column partitions. At the same time, the row and column permutations are carried out for node-processor load balancing. Finally, the authors study the feasibility of simulating large-scale neural networks with 1 million neurons and 10 billion connections using toroidal lattice architecture node processors.<>