Title :
At-speed delay testing of synchronous sequential circuits
Author :
Pomeranz, Irith ; Reddy, Sudhakar M.
Author_Institution :
Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
Abstract :
Methods to test sequential circuits for delay faults are discussed. A method called at-speed testing is proposed for simplifying test application and reducing test length. A value system to allow at-speed testing is developed, and a test generation procedure is presented. The effect of at-speed test application on the path delay fault model is described. Experimental results are presented, demonstrating the applicability of at-speed testing and its effect on test length
Keywords :
delays; fault location; logic testing; sequential circuits; at-speed testing; delay faults; path delay fault model; synchronous sequential circuits; test generation procedure; Circuit faults; Circuit testing; Clocks; Combinational circuits; Delay effects; Flip-flops; Robustness; Sequential analysis; Sequential circuits; System testing;
Conference_Titel :
Design Automation Conference, 1992. Proceedings., 29th ACM/IEEE
Conference_Location :
Anaheim, CA
Print_ISBN :
0-8186-2822-7
DOI :
10.1109/DAC.1992.227840
