4-bit ripple carry adder using two phase clocked adiabatic static CMOS logic

This paper demonstrates the low energy operation of 4-bit ripple carry adder (RCA) employing two phase clocked adiabatic static CMOS logic (2PASCL) circuit techniques. We evaluate NOT, NAND, XOR and NOR logic gates on the basis of the 2PASCL topology using SPICE implemented using 0.18 ¿m CTX CMOS technology. For NOT circuit, analytical and simulation values are compared. By removing the diode from the charging path, higher output amplitude is achieved and the power consumption of the diode is eliminated. From the simulation results, we find that 4-bit 2PASCL RCA can save an average of 71.3% of dissipated energy as compared to that with a static 4-bit CMOS RCA at transition frequencies of 10 to 100 MHz. The results indicates that 2PASCL technology can be advantageously applied to low-power digital devices operated at low frequencies, such as radio-frequency identifications (RFIDs), smart cards, and sensors.