Time partitioning framework for fully reconfigurable systems

The SRAM technologies allow the FPGA device to be reconfigured by loading new configuration data. Real time reconfiguration can be performed by loading each configuration data then reinitializing the device. The entire process (loading and reinitializing) requires less than some milliseconds, which can be used to fit a large application onto the FPGA device by partitioning the application over time. Our first aim in this paper consists of introducing a design flow for reconfigurable systems, the second aim consists of introducing a time partitioning algorithm that divides the input task graph model to an optimal number of partitions and puts each task in the appropriate partition so that the latency of the input task graph is optimal.