DocumentCode
3258640
Title
Representing conditional branches for high-level synthesis applications
Author
Rim, Minjoong ; Jain, Rajiv
Author_Institution
Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
fYear
1992
fDate
8-12 Jun 1992
Firstpage
106
Lastpage
111
Abstract
The authors outline a new representation of behavioral specification for high-level synthesis applications. The main features of the representation are correct handling of conditional branches; the ability to tradeoff between control-select and data-select forms; keeping minimum necessary precedence relationships; correct representation of all conditional actions; and simplified mutual exclusion testing and correct determination of bit-widths and value transfers. The representation is simple and can be easily generated automatically
Keywords
circuit layout CAD; formal specification; behavioral specification; bit-widths; compilers; conditional actions; conditional branches representation; control-select; data flow graphs; data-select forms; high-level synthesis; minimum necessary precedence relationships; mutual exclusion testing; value transfers; Application software; Automatic generation control; Computer languages; Flow graphs; Hardware; High level synthesis; Performance evaluation; Pipeline processing; Resource management; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 1992. Proceedings., 29th ACM/IEEE
Conference_Location
Anaheim, CA
ISSN
0738-100X
Print_ISBN
0-8186-2822-7
Type
conf
DOI
10.1109/DAC.1992.227853
Filename
227853
Link To Document