Incorporating local variables in mixed-signal assertions

In verification of Analog and Mixed-Signal (AMS) designs, considerable efforts are being given now days towards extending assertion languages such as Property Specification Language (PSL) and SystemVerilog Assertions (SVA) to capture mixed-signal behaviors and verify them on mixed-signal design at run-time. In SVA and PSL the temporal properties are written on boolean valued signals only, whereas in the AMS extensions we intend to handle the real valued variables (like voltages, currents etc) by encapsulating them in terms of analog predicates. In this paper we discuss how certain complex mixed-signal properties can be encoded with the help of local variables and describe a methodology for dynamically verifying such AMS properties by mapping them into SVA properties. We demonstrate the proof of concept using our prototype toolkit which parses the AMS properties involving local variables and generates corresponding equivalent SVA properties and Verilog-AMS monitors to verify them dynamically using Synopsys´ mixed-signal simulator Nanosim-VCS along with SVA checker.