Automatic transistor sizing in high performance CMOS logic circuits

The authors present new methods for optimization-based automatic transistor sizing in digital CMOS VLSI circuits. The main novelty of their approach is that complete and accurate solutions of the circuit optimization problem are achieved at low computational costs. Hence complex design problems can be solved. As a practical application of the concepts, a circuit consisting of 11 logic gates is optimized. As a second example, the decoder of a hierarchical 64k-SRAM is considered, where parallel interacting signal paths are critical for timing. Noninferior design alternatives can be obtained by optimizing the different critical signal paths by successive application of the methods