A methodology for parallel synthesis of zero skew differential clock distribution networks

Synthesis of clock distribution network is one of the primary time-consuming steps, performed in the synthesis flow of VLSI systems. With the growth of VLSI systems in advanced technologies, this part has also become more complicated and less computational cost-effective. The objective of this paper is to leverage parallel computing features to reduce computational time for synthesis of clock distribution in the design-flow of VLSI systems. Differential clock distribution networks show acceptable parametric certainty in the presence of environmental variations, and therefore have been considered as a viable solution to reduce the uncertainties caused by process and environmental variations. Based on benchmark results, near-linear speed-up is achieved for zero-skew clock routing, with the proposed parallel algorithm, compared to its sequential counterpart. It is expected that, for very large benchmarks, the speed-up grows linearly when the number of clock sinks is sufficiently large, compared to the number of processing nodes, thus making the overhead due to parallel processing negligible.