A new subthreshold leakage model for NMOS transistor stacks

In this paper, a new model for subthreshold leakage estimation in the UDSM realm is proposed. This model is able to estimate subthreshold leakage in transistor stacks with varying transistor widths. Although only transistor stacks of 2 and 3 transistors are considered, the model can be easily expanded to deal with 4 and 5 transistor stacks. The model achieves this by estimating the stack nodal voltages. Compared to SPICE simulations, the model lead to 3% and 10% average error for the two and three transistor stacks respectively in the 45nm Predictive Technology Model (PTM) process. Slightly lower errors were achieved in the 65nm PTM process.