Efficiency considerations for DT-CNN hardware

Cellular neural networks have become a popular paradigm for modeling nonlinear systems. First-hand implementations are in software on floating-point platforms for pure performance, while programmable analog circuitry has been tested for embedded low-power applications. The paper discusses gradual algorithmic and structural improvements that bring efficient digital hardware into consideration. This provides 32-bits floating-point accuracy on a block-scaled 12-bits fixed-point platform.