Proceedings of the ASP-DAC 2006. Asia and South Pacific Design Automation Conference 2006 (IEEE Cat. No.06EX1199C)

fYear

2006

fDate

24-27 Jan. 2006

Abstract

The following topics are dealt with: formal methods; formal verification; SoC interconnects; timing analysis; integrated circuit design; circuit CAD; integrated circuit layout; nanoscale integrated circuits; logic synthesis; network routing; flash memories; embedded systems; circuit simulation; low power design; circuit optimization; memory and processor architecture; yield analysis and high level synthesis

Keywords

circuit CAD; circuit optimisation; circuit simulation; embedded systems; flash memories; formal verification; high level synthesis; integrated circuit design; integrated circuit interconnections; integrated circuit layout; logic design; low-power electronics; memory architecture; microprocessor chips; nanoelectronics; network routing; system-on-chip; timing; SoC interconnects; circuit CAD; circuit optimization; circuit simulation; embedded systems; flash memories; formal methods; formal verification; high level synthesis; integrated circuit design; integrated circuit layout; logic synthesis; low power design; memory architecture; nanoscale integrated circuits; network routing; processor architecture; timing analysis; yield analysis;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation, 2006. Asia and South Pacific Conference on

Conference_Location

Yokohama

Print_ISBN

0-7803-9451-8

Type

conf

DOI

10.1109/ASPDAC.2006.1594620

Filename

1594620