Constraint-based voltage island partitioning

Among the different methods of reducing power, the voltage island technique is gaining in popularity for core- based SoC design. Assigning cores to the different supply voltages and early voltage island analysis are two key steps in the overall design process. In previous work, each iteration involved a heuristic assignment of cores to voltage islands followed by an expensive floorplanning step. Multiple iterations were required to obtain a solution. However, as the number of cores increases, the floorplanning stage becomes the bottleneck. In this paper, a constraint-based approach is used to identify the best candidates for floorplanning, thus reducing the overall runtime. Starting from a voltage assignment table, we propose a methodology to quickly find an ordered set of feasible voltage assignments. The solutions that satisfy the power constraints are identified and analyzed using a multi- VDd power grid representation to find the optimal amount of decoupling capacitance required to satisfy the supply noise constraint. Next, the solutions that satisfy a total area constraint are selected. Finally, the solutions that satisfy power, area and supply noise constraints are fed to the floorplanner in sorted order until the first acceptable solution is found.