Title :
Full custom design of comparators for LDPC decoder
Author :
Yong-jie, Fan ; Yue-kang, Tan ; Xiao-bo, Jiang
Author_Institution :
Sch. of Electron. & Inf. Eng., South China Univ. of Technol., Guangzhou, China
Abstract :
Comparator is the key module in LDPC decoder that consumes most of the power and area. In this paper, a new comparator based on pass transistors and dynamic logic is proposed to decrease the power and the area. The comparator is implemented with full custom design at SMIC 0.18 1P6M technology. The simulation result of layout shows that the power drops by 11.4% and the area is reduced by 30% compared with the circuit mentioned in reference which we implement with the same technology.
Keywords :
comparators (circuits); decoding; parity check codes; LDPC decoder; SMIC 1P6M technology; comparators; dynamic logic; low density parity check decoder; pass transistors; Asynchronous circuits; Circuit simulation; Decoding; Design engineering; Logic circuits; Logic design; Parity check codes; Power engineering and energy; Signal generators; Transistors;
Conference_Titel :
TENCON 2009 - 2009 IEEE Region 10 Conference
Conference_Location :
Singapore
Print_ISBN :
978-1-4244-4546-2
Electronic_ISBN :
978-1-4244-4547-9
DOI :
10.1109/TENCON.2009.5396206
