Timing-constrained redundant via insertion for yield optimization

According to the equivalent circuit of on-track or off-track redundant via insertion and the timing delay of each net in as the timing constraint, an enhanced timing-constrained two-phase insertion approach for yield optimization is proposed to insert on-track and off-track redundant vias. For the Poisson yield model in redundant via insertion, the experimental results show that our proposed enhanced two-phase insertion approach only reduces 0.003%~0.005% total wire length and 0.0001%~0.0003% chip yield to maintain 100% timing constraints for the tested benchmarks.