Title :
A method for reducing complex MOS structures in switch level simulators
Author :
Aissi, Cherif ; Gobovic, Desa ; Olaniyan, Jide
Author_Institution :
Dept. of Electr. Eng., Howard Univ., Washington, DC, USA
fDate :
27 Nov-1 Dec 1995
Abstract :
A new method is proposed for simplifying complex MOS structures in switch level simulators. It is shown that the well known technique of circuit analysis can be applied to the shape factor “S” of different MOS transistors. This allows an equivalent transistor strength to be easily computed. The obtained results are applicable to both NMOS and CMOS structures. Examples are given to illustrate the use of the method
Keywords :
MOS integrated circuits; VLSI; circuit analysis computing; digital simulation; integrated circuit modelling; CMOS structures; NMOS structures; VLSI; circuit analysis; complex MOS structures; equivalent transistor strength; shape factor; switch level simulators; Circuit analysis; Circuit faults; Circuit simulation; Computational modeling; Intrusion detection; MOSFETs; Shape; Switches; Switching circuits; Threshold voltage;
Conference_Titel :
Physical and Failure Analysis of Integrated Circuits, 1995., Proceedings of the 1995 5th International Symposium on the
Print_ISBN :
0-7803-2797-7
DOI :
10.1109/IPFA.1995.487600
