Design & simulation of a novel 12 bit pipelined analog to digital converter with simplified functional block modules using 0.35µ technology

Analog to Digital converters (ADC) are key design blocks in modern microelectronics communication systems. The fast advancement of CMOS fabrication technology requires more and more signal processing functions which are implemented for lower cost, lower power consumption and higher yield. This has recently generated a great demand for low power, low voltage ADCs. This work presents a new architecture with reduced circuit components and complete circuit realization of its individual circuit blocks. This new architecture applies an indigenous gain stage for multiply by two function particularly used for the subtraction and amplification block. There may be less power dissipation because this proposed pipeline ADC needs only one additional operational amplifier and a comparator compared to traditional one Pipeline A/D architecture. This architecture is analyzed at 0.35μ tsmc technology using Mentor Graphics tool at 3.3 V power supply. Advantages and disadvantages of the architecture are discussed.