CMOS ESD protection structures-characteristics and performance comparison

Author

Fried, Rafael ; Blecher, Yaron ; Friedman, Shimon

Author_Institution

Nat. Semicond. (I.C) Ltd., Herzliya, Israel

fYear

1995

fDate

27 Nov-1 Dec 1995

Firstpage

106

Lastpage

110

Abstract

The performance of ESD protection structures is highly dependent on process parameters, circuit and layout effects, and the structure´s area and geometry. The goal of the work reported here was to produce the best ESD protection structure in a standard 0.8 μm N-well CMOS LDD non-silicided process, under the constraint of a given area that is dictated by the pad´s pitch (132 μm×65 μm), and without adding steps to the process. Basic building blocks of CMOS ESD protection structures are reviewed. Layout and circuit effects are discussed. Several ESD protection structures were tested and their performance was compared. DC characteristics and ESD zapping results are reported. 10 kV HBM ESD protection structures are disclosed

Keywords

CMOS integrated circuits; electrostatic discharge; integrated circuit technology; protection; 0.8 micron; 10 kV; CMOS ESD protection structures; DC characteristics; ESD zapping; N-well CMOS LDD nonsilicided process; Breakdown voltage; CMOS process; Circuit testing; Design for quality; Electrostatic discharge; Fingers; Protection; Stress; Thyristors; Variable structure systems;

fLanguage

English

Publisher

ieee

Conference_Titel

Physical and Failure Analysis of Integrated Circuits, 1995., Proceedings of the 1995 5th International Symposium on the

Print_ISBN

0-7803-2797-7

Type

conf

DOI

10.1109/IPFA.1995.487605

Filename

487605