Title :
A low-cost architecture design with efficient data arrangement and memory configuration for MPEG-2 audio decoder
Author :
Tsai, Tsung-Han ; Chen, Liang-Gee ; Huang, Sheng-Chieh ; Chang, Hao-Chieh
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
fDate :
31 May-3 Jun 1998
Abstract :
The paper describes a low-cost MPEG-2 audio decoder with a modified fast algorithm for decoding. In the modified decoding scheme, the computation amount of the bottleneck module can be reduced into one-forths of the original one. Also, the major memory storage only requires half size of the standard synthesis subband filterbank. The decoder is developed for the approaches of simplicity and low-cost architecture design, with the techniques of intelligent data arrangement and memory configuration
Keywords :
audio coding; audio signals; decoding; discrete cosine transforms; parallel architectures; pipeline processing; storage management; telecommunication standards; MPEG-2 audio decoder; bottleneck module; computation; data arrangement; intelligent data arrangement; low-cost architecture design; memory configuration; standard synthesis subband filterbank; Audio coding; Bit rate; Clocks; Codecs; Decoding; Filter bank; Frequency; Memory; Sampling methods; Standards development;
Conference_Titel :
Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on
Conference_Location :
Monterey, CA
Print_ISBN :
0-7803-4455-3
DOI :
10.1109/ISCAS.1998.698759
