DocumentCode :
3259609
Title :
Test time minimization for system-on-chip with test bus assignment and sizing
Author :
Harmanani, Haidar M. ; Sawan, Rachel
Author_Institution :
Dept. of Comput. Sci. & Math., Lebanese American Univ., Byblos
fYear :
2007
fDate :
5-8 Aug. 2007
Firstpage :
1281
Lastpage :
1284
Abstract :
Test access is a major problem in testing embedded cores as it directly impacts testing time and hardware cost. Test access mechanism (TAM) is responsible for test data transport and is characterized by its bandwidth capacity. Efficient TAM design is of critical importance in SOC system integration since a test architecture should reduce test cost by minimizing test application time. In this paper, we propose a genetic algorithm to design test access architectures while investigating test bus sizing concurrently with assigning cores to test buses. We present experimental results that demonstrate the effectiveness of the proposed method.
Keywords :
genetic algorithms; logic testing; system-on-chip; SoC system; genetic algorithm; system-on-chip; test access mechanism; test time minimization; Algorithm design and analysis; Benchmark testing; Circuit testing; Costs; Genetic algorithms; Hardware; Logic testing; Niobium; System testing; System-on-a-chip;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2007. NEWCAS 2007. IEEE Northeast Workshop on
Conference_Location :
Montreal, Que
Print_ISBN :
978-1-4244-1163-4
Electronic_ISBN :
978-1-4244-1164-1
Type :
conf
DOI :
10.1109/NEWCAS.2007.4488014
Filename :
4488014
Link To Document :
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