DocumentCode :
3259652
Title :
Word level functional coverage computation
Author :
Alizadeh, Bijan
Author_Institution :
Microelectron. R&D Center Iran, Tehran
fYear :
2006
fDate :
24-27 Jan. 2006
Abstract :
This paper proposes word-level coverage metric to determine the completeness of a set of properties verified by a word-level method. An algorithm is presented to compute a functionality based coverage metric for a sequence property as specification. Control, intermediate and output signals are represented by a multiplexer based structure of linear integer equations, and RT level properties are directly applied to this representation. A set of integer equations are symbolically simulated based on the specified property in a predictable time. We used a canonical form of linear Taylor expansion diagram
Keywords :
circuit simulation; formal specification; formal verification; sequential circuits; RT level properties; functional coverage computation; intermediate signals; linear Taylor expansion diagram; linear integer equations; multiplexers; sequence properties; word level coverage computation; word-level coverage metric; Boolean functions; Circuit simulation; Computational modeling; Data structures; Equations; Logic; Microelectronics; Multiplexing; Research and development; Taylor series;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation, 2006. Asia and South Pacific Conference on
Conference_Location :
Yokohama
Print_ISBN :
0-7803-9451-8
Type :
conf
DOI :
10.1109/ASPDAC.2006.1594637
Filename :
1594637
Link To Document :
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