A single-chip ring-based multiprocessor with region-level filtering of coherence traffic

This paper presents the architecture and prototype hardware implementation of a single-chip shared-memory multiprocessor based on a ring interconnect with support for adaptive filtering of coherence traffic. Our implementation is suitable for application-specific designs and avoids the complexity associated with directory-based cache coherence by limiting writes to addresses that are local to the requesting node while maintaining cache coherence for shared data throughout the system. In addition, we seek to adaptively restrict the scope of coherence operations by employing filter structures in hardware with modest storage requirements. To characterize the logic utilization of the proposed filters relative to other system components, a prototype multiprocessor system has been described in 4250 lines of synthesizable SystemVerilog code and implemented in field-programmable logic. Synthesis results are presented to characterize the logic overhead of the filter structures, and operational results are presented to demonstrate their behavior.