Performance enhancement and high-level specification of a pipelined processor in programmable logic

This paper describes the performance enhancement of a custom pipelined processor in programmable logic, and the description of the enhanced processor with the higher- level specification syntax of a custom software tool for system implementation in hardware. Faster operation of the processor is enabled with a revised clocking scheme for the embedded memory blocks that are used for the register file and the caches. A higher-level implementation of the enhanced processor is specified with a custom software tool called QUI²VER (Queen´s University Interface Integrator in VHDL for Education and Research) that generates VHDL output. Synthesis results obtained with Altera Quartus II for a Stratix chip characterize the modest overhead for the datapath modifications to support the revised clocking scheme in the enhanced processor datapath. Results from timing analysis indicate an increase in the processor clock frequency by 76% relative to the previous implementation.