DocumentCode :
3259726
Title :
On the design of incremental ∑Δ converters
Author :
Belloni, M. ; Fiore, C. Della ; Maloberti, F. ; Andrade, M. García
Author_Institution :
Dept. of Electron., Univ. of Pavia, Pavia
fYear :
2007
fDate :
5-8 Aug. 2007
Firstpage :
1376
Lastpage :
1379
Abstract :
The theoretical basis and design techniques of incremental converters for obtaining optimum performances are presented. The most suitable architectures and signal processing are identified. They allow to limit the loss of resolution caused by active components with finite gain and bandwidth. Matching of elements that enables the use of multi-bit quantizers is also discussed.
Keywords :
quantisation (signal); signal processing; incremental SigmaDelta converters design techniques; multibit quantizers; signal processing; Amplitude modulation; Bandwidth; Circuits; Clocks; Costs; Delta-sigma modulation; Frequency domain analysis; Limit-cycles; Signal processing; Signal resolution;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2007. NEWCAS 2007. IEEE Northeast Workshop on
Conference_Location :
Montreal, Que
Print_ISBN :
978-1-4244-1163-4
Electronic_ISBN :
978-1-4244-1164-1
Type :
conf
DOI :
10.1109/NEWCAS.2007.4488019
Filename :
4488019
Link To Document :
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