Title :
Analyzing memory bandwidth requirements of video algorithms
Author_Institution :
DSPS R&D Center, Texas Instrum. Inc., Dallas, TX, USA
fDate :
31 May-3 Jun 1998
Abstract :
Memory bandwidth is emerging as the fundamental impediment to higher performance and lower power computer and communication systems. In this paper, we present an analysis of memory bandwidth requirements for the H.263 video codec algorithms. We make use of memory traces generated as a result of running Telenor´s H.263 video encoder and decoder software implementations to simulate a large number of cache configurations. In the area of analysis of video algorithms, this paper focuses on the following issues: We provide a study of how varying cache size, block size, associativity, replacement policy, and organization parameters such as split versus unified cache affects memory bandwidth requirements. A comparative study of encoder and decoder bandwidth requirements is presented. We also study various advanced encoding options provided with the H.263 standard in this light. Based on our study, we provide guidelines for traffic-directed memory system design
Keywords :
decoding; digital simulation; encoding; telecommunication computing; telecommunication standards; video codecs; H.263 standard; H.263 video codec algorithms; Telenor´s H.263 video encoder; advanced encoding options; analysis; associativity; block size; cache configurations; cache size; decoder; memory bandwidth requirements; simulation; software implementation; traffic-directed memory system design; video algorithms; Algorithm design and analysis; Bandwidth; Decoding; Delay; Digital signal processing; Energy consumption; Impedance; Random access memory; Signal processing algorithms; System-on-a-chip;
Conference_Titel :
Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on
Conference_Location :
Monterey, CA
Print_ISBN :
0-7803-4455-3
DOI :
10.1109/ISCAS.1998.698786
