MPEG-4 accelerator for PC based codec implementation

In the MPEG-4 world, a scene is described as a composition of independent audiovisual objects that the user can access and manipulate. The MPEG-4 video being currently standardized will provide a toolbox containing tools and algorithms bringing solutions enabling functionality. So it is very difficult to satisfy the various MPEG-4 video requirements using dedicated hardwares. In this paper we propose a flexible and high performance hardware architecture using DSP in conjunction with an MEMC (Motion Estimation and Motion Compensation) ASIC chip to implement MPEG-4 video codec. We developed the MEMC chip for an MPEG-2 MP@ML encoder. In order to see if it is possible to adopt the MEMC chip for the MPEG-4 accelerator, we simulated a modified MPEG-4 Video VM (Verification Model). The results of computer simulation showed that we can adopt the MEMC chip to implement MPEG-4 video