Design and implementation of a fully testable CMOS D-latch

Author

Aissi, Cherif ; Olaniyan, Jide

Author_Institution

Dept. of Electr. Eng., Howard Univ., Washington, DC, USA

fYear

1995

fDate

27 Nov-1 Dec 1995

Firstpage

194

Lastpage

199

Abstract

A fully testable CMOS D-latch (FTD) is proposed. Earlier work had considered D-latches testable by only a limited set of faults. In this paper, a comprehensive test set is developed. This test set is then applied to the FTD. The cost of implementation, analysis and simulation of the FTD are all carried out. Application of the FTD-latch to build a polarity-hold shift register is shown

Keywords

CMOS logic circuits; automatic testing; flip-flops; logic testing; sequential circuits; shift registers; circuit simulation; comprehensive test set; fault testing; fully testable CMOS D-latch; polarity-hold shift register; sequential circuit testing; synchronous sequential circuits; CMOS logic circuits; Circuit faults; Circuit testing; Costs; Electrical fault detection; Integrated circuit interconnections; Latches; Sequential analysis; Sequential circuits; Shift registers;

fLanguage

English

Publisher

ieee

Conference_Titel

Physical and Failure Analysis of Integrated Circuits, 1995., Proceedings of the 1995 5th International Symposium on the

Print_ISBN

0-7803-2797-7

Type

conf

DOI

10.1109/IPFA.1995.487622

Filename

487622

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3259847