Design techniques for high speed current steering DACs

This paper proposes an optimized latch circuit with embedded delays and a new method to ensure robust synchronization in presence of mismatches that is very useful in the design of high-speed current steering digital to analog converters (DACs). The proposed circuit is validated as part of a 10 bit 100 MHz DAC designed using a standard 180 nm CMOS process. The measured integral nonlinearity lies between -0.42LSB and 0.68LSB and the measured differential nonlinearity is better than 0.73 LSB. The layout occupies 390 mum* 538 mum core area. The DAC operates from 3.3-V power supply and produces 16.5 mA full swing output current. At 100 MS/s, a measured spurious free dynamic range (SFDR) of 66 dB has been obtained for a 2 MHz input signal.