Poly-3 bitline crack [DRAMs]

The increasing trend in cold temperature failures has reached a high level and the predominant fail label is LRAS:RMW. Electrical Failure Analysis (EFA) of Pre (T1) & Post (T2) burn-in ADSEL and XMC failures revealed a consistent pattern of bits that failed along a column. Through the understanding of the device layout, a poly-3 bitline twist crack fault model is proposed and confirmed subsequently through Physical Failure Analysis (PFA). As an extension to this finding, electrical characterization of LRAS:RMW C/T failures also showed the same failmode, though of lesser severity. An effective guardband test is developed at room temp to screen out this category of failure. This test achieved minimal impact to overall testtime and overkill. Process & design actions were initiated at Waferfab & Design to resolve the poly-3 crack issue, with preliminary evaluation data showing promising results. A short discussion of the lessons learnt is included, in particular the fanning out of waferfab & design changes to other device type using the same bitline twist architecture