An LPC cepstrum processor for speech recognition

Author

In-Chul Hwang ; Kim, Sung-Nam ; Kim, Young-Woo ; Kim, Soo-Won

Author_Institution

ASIC Design Tech. Lab., Korea Univ., Seoul, South Korea

Volume

4

fYear

1998

fDate

31 May-3 Jun 1998

Firstpage

233

Abstract

An LPC cepstrum processor for speech recognition is implemented on CMOS gate array. The processor that we designed contains a 24 bit floating-point MAC unit, which computes a correlation rapidly, the majority of operations in the algorithm. This processor has 22 register files to store temporary variables, which enable one to reduce access to external memory. For the purpose of fast operations, the floating-point MAC consists of a pipeline structure with 3 stages and uses a branched postnormalization scheme proposed in this paper. Experimental results show that it takes approximately 266 μs to process a frame of 20 ms at 15 MHz clock rate. This processor runs at the maximum rate of 16.6 MHz and the number of transistors is 55,520

Keywords

CMOS logic circuits; cepstral analysis; linear predictive coding; logic arrays; pipeline processing; speech recognition; 15 MHz; 266 mus; CMOS gate array; LPC cepstrum processor; branched postnormalization scheme; clock rate; floating-point MAC unit; pipeline structure; speech recognition; temporary variables; Application specific integrated circuits; Autocorrelation; CMOS process; Cepstrum; Clocks; Linear predictive coding; Pipelines; Process design; Registers; Speech recognition;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on

Conference_Location

Monterey, CA

Print_ISBN

0-7803-4455-3

Type

conf

DOI

10.1109/ISCAS.1998.698802

Filename

698802