• DocumentCode
    3259947
  • Title

    A low dynamic power and low leakage power 90-nm CMOS square-root circuit

  • Author

    Enomoto, Tadayoshi ; Kobayashi, Nobuaki

  • Author_Institution
    Graduate Sch. of Sci. & Eng., Chuo Univ., Tokyo, Japan
  • fYear
    2006
  • fDate
    24-27 Jan. 2006
  • Abstract
    To drastically reduce the dynamic power (PAT) and the leakage power (PST), while to keep speed of a CMOS square-root (SR) circuit, a new algorithm, new architectures and a new leakage reduction circuit were developed. Using these techniques, a 90-nm CMOS LSI was fabricated. The PAT and PST of the new SR circuit were reduced to about 1/4 and 1/33 those of a conventional SR circuit. Measured results agreed well with simulated results.
  • Keywords
    CMOS integrated circuits; large scale integration; leakage currents; low-power electronics; 90 nm; CMOS LSI; CMOS square-root circuit; SR circuit; dynamic power; leakage power; leakage reduction circuit; Adders; CMOS logic circuits; CMOS technology; Equations; Leakage current; Logic gates; Power engineering and energy; Strontium; Systems engineering and theory; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation, 2006. Asia and South Pacific Conference on
  • Print_ISBN
    0-7803-9451-8
  • Type

    conf

  • DOI
    10.1109/ASPDAC.2006.1594651
  • Filename
    1594651
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3259947