Title :
Resource efficient 64-bit floating point matrix multiplication algorithm using FPGA
Author :
Sonawane, D.N. ; Sutaone, M.S. ; Malek, Inayat
Author_Institution :
Dept. of Instrum. & Control, Coll. of Eng., Pune, Pune, India
Abstract :
The paper presents a novel methodology to implement resource efficient 64-bit floating point matrix multiplication algorithm using FPGA. Approach uses systolic architecture using four processing element (PE´s) that gives tradeoffs between resource utilization and execution time, results in reducing the routing complexity for dense matrix multiplication problems.
Keywords :
circuit complexity; field programmable gate arrays; matrix multiplication; FPGA; floating point matrix multiplication algorithm; processing element; routing complexity; systolic architecture; Buffer storage; Clocks; Digital signal processing; Educational institutions; Field programmable gate arrays; Instruments; Resource management; Routing; Signal processing algorithms; Telecommunication control; Systolic architecture; Virtex-5; matrix multiplication; processing element (PE);
Conference_Titel :
TENCON 2009 - 2009 IEEE Region 10 Conference
Conference_Location :
Singapore
Print_ISBN :
978-1-4244-4546-2
Electronic_ISBN :
978-1-4244-4547-9
DOI :
10.1109/TENCON.2009.5396236
