A proposed symmetric and balanced 11-T SRAM cell for lower power consumption

Static random access memories (SRAMs) comprise an increasingly large portion of modern very large scale integrated (VLSI) circuits. The increasing importance of embedded SRAM is due to its low circuit activity factor, leading to low active power density, and productivity of design. The power consumption has become an important issue and has lead to the development of numerous schemes aimed at limiting that component of power during both standby and active operation. In the present paper, we have proposed a symmetric 11-T SRAM cell to reduce power consumption during read/write operation. We have simulated the designed circuit with the help of Tanner EDA tools for 0.25 ¿m technology and simulated results were compared with 6T and ZA cell. It was found that proposed cell consumes 28% lower power than conventional 6T during write mode. During read operation, the average power saving is around 33% compared to conventional cell. The write delay is more in our proposed cell. By choosing width of tail transistors are equal to 3 ¿m, the write delay of the proposed cell can be equated to conventional cell.