DocumentCode
3260159
Title
High-throughput decoder for low-density parity-check code
Author
Ishikawa, Tatsuyuki ; Shimizu, Kazunori ; Ikenaga, Takeshi ; Goto, Satoshi
Author_Institution
Graduate Sch. of Inf., Production & Syst., Waseda Univ., Fukuoka
fYear
2006
fDate
24-27 Jan. 2006
Abstract
We have designed and implemented the LDPC decoder chip with memory-reduction method to achieve high-throughput and practical chip size. The decoder decodes (3,6)-2304 bit regular LDPC codes using modified min-sum algorithm. The decoder achieves a throughput of 530Mb/s at an operating frequency of 147MHz. The chip has been fabricated in a 0.18mum, 6 metal-layer CMOS technology. The chip size is 36mm2
Keywords
CMOS integrated circuits; decoding; integrated circuit design; parity check codes; 0.18 micron; 147 MHz; 530 Mbit/s; CMOS technology; decoder chip; decoding; low density parity check code; memory-reduction method; min-sum algorithm; CMOS technology; Frequency; Hardware; Iterative algorithms; Iterative decoding; Parity check codes; Production systems; Random access memory; Throughput; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation, 2006. Asia and South Pacific Conference on
Conference_Location
Yokohama
Print_ISBN
0-7803-9451-8
Type
conf
DOI
10.1109/ASPDAC.2006.1594662
Filename
1594662
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