Easy simulation and design of on-chip inductors in standard CMOS processes

Author

Christensen, Kåre T. ; Jorgensen, Allan

Author_Institution

Center for Integrated Electron., Tech. Univ. Denmark, Lyngby, Denmark

Volume

4

fYear

1998

fDate

31 May-3 Jun 1998

Firstpage

360

Abstract

This paper presents an approach to CMOS inductor modelling, that allow easy simulation in SPICE-like simulators. A number of test results are presented concerning optimal center hole, inductor area, wire spacing and self-inductance. Finally a comprehensive design guide is provided on how to design close-to-optimal inductors without the use of electromagnetic simulators

Keywords

CMOS integrated circuits; SPICE; eddy currents; inductance; inductors; integrated circuit design; integrated circuit modelling; lumped parameter networks; CMOS inductor modelling; SPICE-like simulators; close-to-optimal inductors; design guide; eddy currents; inductor area; lumped element model; multilayer inductors; on-chip inductors; optimal center hole; parasitics; self-inductance; simulation; standard CMOS processes; wire spacing; CMOS process; Conductivity; Eddy currents; Frequency dependence; Inductance; Inductors; Predictive models; Resistors; Semiconductor device modeling; Silicon;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on

Conference_Location

Monterey, CA

Print_ISBN

0-7803-4455-3

Type

conf

DOI

10.1109/ISCAS.1998.698855

Filename

698855