Analysis of an associative array parallel logic simulator

This paper details the architecture and performance of an innovative hardware logic simulator for logic event-driven simulation, APPLES (Associative Parallel Processor for Logic Event Simulation). Although event-driven, the design obviates the need for an event-list and scheduling. Furthermore, the gate evaluation phase of the simulation cycle is constant in time, regardless of the circuit being simulated. The process of up-dating the fan-out lists is accomplished through a scanning mechanism. The time complexity of this mechanism expands in proportion to the number of gates being simulated, however it is highly adaptable to parallelisation. The speedup performance and gate execution rate of APPLES exceeds that of conventional hardware logic simulators, yet it maintains all the of a traditional software event-driven simulator. This is demonstrated in the extensive repertoire of delay models that may be simulated and the performance displayed by a Verilog version of APPLES on several ISCAS-85 benchmarks