Implementation of H.264/AVC decoder for mobile video applications

Author

Lee, Suh Ho ; Park, Ji Hwan ; Kim, Seon Wook ; Ko, Sung Jea ; Kim, Suki

Author_Institution

Dept. of Electron. & Comput. Eng., Korea Univ., Seoul, South Korea

fYear

2006

fDate

24-27 Jan. 2006

Abstract

This paper presents an H.264/AVC baseline profile decoder based on a SoC platform design methodology. The overall decoding throughput is increased by optimized software and a dedicated hardware accelerator. We minimize the number of bus accesses and use macroblock (MB) level pipeline processing techniques to achieve a real time operation. We implemented and verified a prototype on a SoC platform with a 32-bit RISC CPU core and FPGA module. Our design can process up to 20 frames/sec with QCIF (176×144). The proposed architecture can be easily applied to many mobile video application areas such as a digital camera and a DMB (digital multimedia broadcasting) phone.

Keywords

decoding; field programmable gate arrays; pipeline processing; reduced instruction set computing; system-on-chip; video coding; FPGA module; H.264/AVC decoder; RISC CPU core; SoC platform design; decoding; digital camera; digital multimedia broadcasting phone; mobile video; pipeline processing techniques; Application software; Automatic voltage control; Decoding; Design methodology; Digital multimedia broadcasting; Hardware; Pipeline processing; Prototypes; Software prototyping; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation, 2006. Asia and South Pacific Conference on

Print_ISBN

0-7803-9451-8

Type

conf

DOI

10.1109/ASPDAC.2006.1594666

Filename

1594666