• DocumentCode
    3260519
  • Title

    Timing-driven placement based on monotone cell ordering constraints

  • Author

    Hwang, Chanseok ; Pedram, Massoud

  • Author_Institution
    Dept. of Electr. Eng.-Syst., Southern California Univ., Los Angeles, CA, USA
  • fYear
    2006
  • fDate
    24-27 Jan. 2006
  • Abstract
    In this paper, we present a new timing-driven placement algorithm, which attempts to minimize zigzags and crisscrosses on the timing-critical paths of a circuit. We observed that most of the paths that cause timing problems in the circuit meander outside the minimum bounding box of the start and end nodes of the path. To limit this undesirable behavior, we impose a physical constraint on the placement problem, i.e., we assign a preferred signal direction to each critical path in the circuit. Starting from an initial placement solution, by using a move-based optimization strategy, these preferred directions force cells to move in a direction that maximizes the monotonic behavior of the timing-critical paths in the new placement solution. To make the direction assignment tractable, we implicitly group all circuit paths into a set of input-output conduits and assign a unique preferred direction to each such conduit. We integrated this idea into a recursive bipartitioning-based placement framework with a min-cut objective function. Experimental results on a set of standard placement benchmarks show that this approach improves the result of a state-of-the-art industrial placement tool for all the benchmark circuits while increasing the wire length by a tolerable amount.
  • Keywords
    circuit CAD; integrated circuit design; timing; benchmark circuits; circuit timing-critical paths; industrial placement tool; input-output conduits; min-cut objective function; monotone cell ordering constraints; move-based optimization strategy; recursive bipartitioning-based placement framework; signal direction; timing-driven placement; Algorithm design and analysis; Circuit analysis; Delay; Integrated circuit interconnections; Logic circuits; Research and development; Signal analysis; Signal processing; Timing; Wire;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation, 2006. Asia and South Pacific Conference on
  • Print_ISBN
    0-7803-9451-8
  • Type

    conf

  • DOI
    10.1109/ASPDAC.2006.1594682
  • Filename
    1594682