Using standard-cell design methodologies on a gate-array base

Gate-array designs normally require larger chip area than equivalent standard-cell designs. However, as netlists get larger routing becomes more important. In this paper, standard-cell channel routing is used to reduce the chip area of a specially designed 0.8 μm gate-array architecture. For very large netlists, results show that gate-array designs can have equal chip area and performance to standard-cell designs