A VLSI chip set for a massively parallel scientific processor

Author

Tripiccione, R.

Author_Institution

INFN, Pisa, Italy

fYear

1992

fDate

1-5 Jun 1992

Firstpage

378

Lastpage

380

Abstract

The author describes a chip set developed to provide basic building blocks for the APE100 massively parallel SIMD (Single Instruction Multiple Data) processor, designed with ASIC techniques and fabricated in a 1.2 μm CMOS technology. This chip set contains three devices, which provide three main functions for a SIMD machine, namely the processing element, the controller for the array of processing nodes and the handling of communication among nodes. These functions are respectively provided by the MAD chip (the processing node), the z Cpu chip (the controller) and the Commuter chip (communication handler)

Keywords

CMOS integrated circuits; VLSI; application specific integrated circuits; microprocessor chips; parallel architectures; parallel machines; 1.2 micron; APE100; ASIC; CMOS technology; Commuter chip; MAD chip; SIMD machine; Single Instruction Multiple Data; VLSI chip set; communication handler; controller; massively parallel scientific processor; processing node; zCpu chip; Application specific integrated circuits; CMOS process; CMOS technology; Collaboration; Communication system control; Concurrent computing; Design optimization; Physics computing; Process design; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Euro ASIC '92, Proceedings.

Conference_Location

Paris

Print_ISBN

0-8186-2845-6

Type

conf

DOI

10.1109/EUASIC.1992.227997

Filename

227997