DocumentCode :
3260821
Title :
A fast methodology for first-time-correct design of PLLs using nonlinear phase-domain VCO macromodels
Author :
Goyal, Prashant ; Lai, Xiaolue ; Roychowdhury, Jaijeet
Author_Institution :
Indian Inst. of Technol., Kanpur, India
fYear :
2006
fDate :
24-27 Jan. 2006
Abstract :
We present a novel methodology suitable for fast, correct design of modern PLLs. The central feature of the methodology is its use of accurate, nonlinear behavioral models for the VCO within the PLL, thus removing the need for many time-consuming SPICE-level simulations during the design process. We apply the new methodology to design a novel injection-aided PLL that acquires lock 3× faster than prior designs, without trading off other design metrics such as jitter. We demonstrate how existing design methodologies based on behavioral simulation are incapable of leading to our new PLL design. The nonlinear behavioral simulations employed in our methodology are about 2 orders of magnitude faster than transistor-level ones, resulting in an overall design productivity gain of an order of magnitude.
Keywords :
circuit simulation; jitter; network synthesis; phase locked loops; voltage-controlled oscillators; first-time-correct design; nonlinear behavioral simulations; nonlinear phase-domain VCO macromodels; phase locked loop design; voltage controlled oscillators; Cities and towns; Clocks; Design methodology; Jitter; Phase locked loops; Predictive models; Process design; Productivity; Transceivers; Voltage-controlled oscillators;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation, 2006. Asia and South Pacific Conference on
Print_ISBN :
0-7803-9451-8
Type :
conf
DOI :
10.1109/ASPDAC.2006.1594697
Filename :
1594697
Link To Document :
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